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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3 ,4 ,5 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK) * * * * * * * Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball(x8), 84ball(x16) FBGA 67.60 x 30.00 mm form factor Lead-free Products are RoHS compliant
* * * * *
ORDERING INFORMATION
Part Name HYMP532S646-E3/C4 HYMP564S648-E3/C4 HYMP564S646-E3/C4 HYMP112S64M8-E3/C4 HYMP532S64P6-E3/C4 HYMP564S64P8-E3/C4 HYMP564S64P6-E3/C4 HYMP112S64MP8-E3/C4 Density 256MB 512MB 512MB 1GB 256MB 512MB 512MB 1GB Organization 32Mx64 64Mx64 64Mx64 128Mx64 32Mx64 64Mx64 64Mx64 128Mx64 # of DRAMs 4 8 8 16 4 8 8 16 # of ranks 1 1 2 2 1 1 2 2 Materials Leaded Leaded Leaded Leaded Lead free Lead free Lead free Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1
1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 400 3-3-3 C4 (DDR2-533) 400 533 4-4-4 Unit Mbps Mbps Mbps tCK
ADDRESS TABLE
Density 256MB 512MB 512MB 1GB Organization Ranks 32M x 64 64M x 64 64M x 64 128M x 64 1 2 1 2 SDRAMs 32Mb x 16 64Mb x 8 32Mb x 16 64Mb x 8 # of DRAMs 4 8 8 16 # of row/bank/column Address 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms
Rev. 1.0 / Feb. 2005
2
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION
Symbol Type Polarity Cross Point Pin Description The system clock inputs. All adress an commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be excecuted by the SDRAM. Selects which DDR2 SDRAM internal bank of four is activated. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data Input/Output pins. Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately. Power supplies for core, I/O, Serial Presense Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. Address pins used to select the Serial Presence Detect base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SODIMMs).
CK[1:0], CK[1:0]
Input
CKE[1:0]
Input
Active High
S[1:0]
Input
Active Low Active Low
RAS, CAS, WE BA[1:0] ODT[1:0]
Input Input Input
A[9:0], A10/AP, A[15:11]
Input
DQ[63:0] DM[7:0]
In/Out Input
DQS[7:0], DQS[7:0] In/Out
Cross point
VDD, VDDSPD,VSS SDA SCL SA[1:0] TEST
Supply In/Out Input Input In/Out
Rev. 1.0 / Feb. 2005
3
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN ASSIGNMENT
Pin NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front Side VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2 Pin NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back Side VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin NO. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front Side DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 Pin NO. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back Side DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 Pin NO. 101 103 105 107 109 111 113 115 117 121 123 125 127 131 133 135 137 139 141 143 145 147 149 Front Side A1 VDD A10/AP BA0 WE VDD CAS NC/S1 VDD VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin NO. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Back Side A0 VDD BA1 RAS S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS Pin NO. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Pin NO. 152 154 156 158 160 162 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1
NC,TEST 164
119 NC/ODT1
NC/CKE1 129
Pin Location
2
40 42
200
Front
1 39 41 199
Back
Rev. 1.0 / Feb. 2005
4
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532S646-E3/C4
/S 1
N .C .
O D T1
N .C .
3 + /- 5 %
CKE0 ODT0 /S 0
CKE1
N .C .
DQS0 /D Q S 0 DM0
LDQS /U D Q S LDM
/C S
ODT
CKE
DQS4 /D Q S 4 DM4
LDQS /L D Q S LDM
/C S
ODT
CKE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I /O 7
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS5 /D Q S 5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
/C S ODT CKE
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D2
DQS1 /D Q S 1 DM1 DQ8 DQ8 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ15
UDQS /U D Q S UDM
UDQS /U D Q S UDM I/O 8 I/O 9 I/O 1 0 I/O 1 1 I/O 1 2 I/O 1 3 I/O 1 4 I /O 1 5
I/O 8 I/O 9 I/O 1 0 I/O 1 1 I/O 1 2 I/O 1 3 I/O 1 4 I /O 1 5
DQS2 /D Q S 2 DM2
LDQS /L D Q S LDM
DQS6 /D Q S 6 DM6
LDQS /L D Q S LDM
/C S
ODT
CKE
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQS3 /D Q S 3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS /U D Q S UDM
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQS7 /D Q S 7 DM7
D3
UDQS /U D Q S UDM
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
I/O 8 I/O 9 I /O 1 0 I /O 1 1 I /O 1 2 I /O 1 3 I /O 1 4 I/O 1 5
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
I /O 8 I /O 9 I/O 1 0 I/O 1 1 I/O 1 2 I/O 1 3 I/O 1 4 I/ O 1 5
3 + /- 5 %
B A 0 -B A 1 A 0 -A N /R A S /C A S /W E
SCL
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
D 0 -3 D 0 -3 D 0 -3 D 0 -3 D 0 -3
SA0 SA1
SCL A0 A1 A2
SDA S e r ia l P D WP
SDA
VDD SP D
CK0
2 lo a d s
S e r ia l P D S D R A M S D O -D 3
V REF VDD
/C K 0
S D R A M S D O -D 3 , V D D a n d V D D Q S D R A M S D O -D 3 , S P D
CK1
2 lo a d s
VSS
/C K 1
N o te s : 1 . R e s is to r v a lu e s a r e 2 2 O h m + /- 5 %
Rev. 1.0 / Feb. 2005
5
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx64) : HYMP564S648-E3/C4
/S 1
N .C .
ODT1
N .C .
3 + /- 5 %
CKE0 ODT0 DQS0
CKE1
N .C .
DQS0 /D Q S 0 DM0
DQS /D Q S DM
/C S
ODT
CKE
DQS4 /D Q S 4 DM4
DQS /D Q S DM
/C S
ODT
CKE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ38 DQ39
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQS /D Q S DM
D4
DQS1 /D Q S 1 DM1
DQS /D Q S DM
/C S
ODT
CKE
DQS5 /D Q S 5 DM5
/C S
ODT
CKE
DQ8 DQ8 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 D Q 15
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DQS2 /D Q S 2 DM2
DQS /D Q S DM
/C S
ODT
CKE
DQS6 /D Q S 6 DM6
DQS /D Q S DM
/C S
ODT
CKE
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 D Q 23
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DQS3 /D Q S 3 DM3
DQS /D Q S DM
/C S
ODT
CKE
DQS0 /D Q S 0 DM0
DQS /D Q S DM
/C S
ODT
CKE
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 D Q 31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
3 + /- 5 %
B A 0 -B A 1 A 0 -A N /R A S /C A S /W E
SCL
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
D 0 -7 D 0 -7 D 0 -7 D 0 -7 D 0 -7
SA0 SA1
SCL A0 A1 A2
SDA S e r ia l P D WP
SDA
VDD S P D V REF
CK0
4 lo a d s
S e r ia l P D S D R A M S D O -D 7
/C K 0
VDD VSS
S D R A M S D O -D 7 , V D D a n d V D D Q S D R A M S D O -D 7 , S P D
CK1
4 lo a d s
/C K 1
N o te s : 1 . R e s is to r v a lu e s a re 2 2 O h m + /- 5 %
Rev. 1.0 / Feb. 2005
6
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx64): HYMP564S646-E3/C4
3 +/- 5 %
O DT 1 O DT 0 CKE 1
CKE 0 /S 1 /S 0
DQ S 0 / DQ S 0 DM 0
LDQ S / UDQ S LDM
/ CS
LDQ S / UDQ S LDM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5
/ CS
DQ S 4 / DQ S 4 DM 4
LDQ S / UDQ S LDM
/ CS
LDQS / UDQ S LDM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5
/ CS
CKE
CKE
CKE
CKE
ODT
ODT
ODT
ODT
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 UDQS / UDQ S UDM
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
DQ S 5 / DQ S 5 DM 5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 UDQ S / UDQ S UDM
D0
I/ O 6 I/ O 7 UDQ S / UDQ S UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
D4
D2
I/ O 6 I/ O 7 UDQ S / UDQ S UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
D6
DQ S 1 / DQ S 1 DM 1 DQ 8 DQ 8 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
DQ S 2 / DQ S 2 DM 2
LDQ S / CS / LDQS LDM
LDQ S / UDQ S LDM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5
/ CS
DQ S 6 / DQ S 6 DM 6
LDQ S / CS / LDQ S LDM
CKE
CKE
ODT
ODT
LDQS / UDQ S LDM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5
/ CS
CKE
CKE
ODT
ODT
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQ S 3 / DQ S 3 DM 3
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 UDQ S / UDQ S UDM
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 UDQ S / UDQ S UDM
D1
I/ O 6 I/ O 7 UDQ S / UDQ S UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
D5
DQ S 7 / DQ S 7 DM 7
D3
I/ O 6 I/ O 7 UDQ S / UDQ S UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
D7
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15
3 +/- 5 % BA0 - BA1 A 0- AN / RAS / CAS /WE
SDRAM S SDRAM S SDRAM S SDRAM S SDRAM S
D 0 -7 D 0 -7 D 0 -7 D 0 -7 D 0 -7
SCL
SA 0 SA 1
SCL A0 A1 A2
SDA Serial PD WP
SDA
Notes : 1. Resistor values are 22 Ohm +/- 5%
Serial PD SDRAM S DO -D 3
CK0
4 loads
V DD SPD V REF V DD
4 loads
/ CK 0
CK 1 / CK 1
SDRAM S DO - D 3 , V DD and V DD Q SDRAM S DO - D 3 , SPD
V SS
Rev. 1.0 / Feb. 2005
7
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) : HYMP112S64M8-E3/C4
3 +/- 5 %
CKE 1 ODT 1 /S1
CKE 0 ODT 0 /S 0
DQS 0 / DQ S 0 DM 0
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQS 1 / DQS 1 DM 1
DQ 8 DQ 8 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQS 2 / DQS 2 DM 2
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQS 3 / DQS 3 DM 3
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
DQS / DQS DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQ S DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQ S DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQ S DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
DQS 4 / DQS 4 DM 4
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
DQS / DQS DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
D 0, D 8 ( DDP )
D 4 ,D 12 ( DDP )
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
DQ S 5 / DQ S 5 DM 5
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQS / DQS DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS DM
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
D 1, D 9 ( DDP )
D 5, D 13 ( DDP )
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
DQ S 6 / DQ S 6 DM 6
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DQS / DQS DM
/ CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1
D 2 , D 10 ( DDP )
D 6,D 14 ( DDP )
/ CS 0 ODT 0 CKE 0
/ CS 1 ODT 1 CKE 1
DQ S 7 / DQ S 7 DM 7
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D 3 , D 11 ( DDP )
D 7,D 15 ( DDP )
SCL
10+/-5 % BA0 - BA1 A 0 - AN / RAS / CAS / WE
SDRAM S SDRAM S SDRAM S SDRAM S SDRAM S D 0 - 15 D 0 - 15 D 0 - 15 D 0 - 15 D 0 - 15
V DD SPD V REF V DD V SS
SA 0 SA 1
SCL A0 A1 A2
SDA Serial PD WP
SDA
:
CK0
9.1 pF
8 loads
8 loads 8 loads
9.1 pF
Serial PD SDRAMS DO - D 15
SDRAMS DO - D 15 , V DD and V DD Q SDRAMS DO - D 15 , SPD
/CK0
CK1
/CK1
Notes : 1. Resistor values are 22 Ohm +/- 5%
8 loads
Rev. 1.0 / Feb. 2005
8
1200pin Unbuffered DDR2 SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Storage Humidity(without condensation) Notes: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. Symbol VDD VDDQ VIN, VOUT TSTG HSTG Value - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -50 ~ +100 5 to 95 Unit V V V
o
Note 1 1 1 1 1
C
%
OPERATING CONDITIONS
Parameter DIMM Operating temperature(ambient) DIMM Barometric Pressure(operating & storage) DRAM Component Case Temperature Range Notes: 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. Symbol TOPR PBAR TCASE Rating 0 ~ +55 105 to 69 0 ~+95 Units
o
Notes 1 2
C
K Pascal
o
C
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter Power Supply Voltage Input Reference Voltage EEPROM Supply Voltage Termination Voltage Symbol VDD VDDQ VREF VDDSPD VTT Min 1.7 1.7 0.49 x VDDQ 1.7 VREF-0.04 Max 1.9 1.9 0.51 x VDDQ 3.6 VREF+0.04 Unit V V V V V 3 1 2 Note
Notes: 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device.
Rev. 1.0 / Feb. 2005
9
1200pin Unbuffered DDR2 SDRAM SO-DIMMs INPUT DC LOGIC LEVEL
Parameter Input High Voltage Input Low Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note
INPUT AC LOGIC LEVEL
Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V Note
AC INPUT TEST CONDITIONS
Symbol VREF VSWING(MAX) SLEW Notes: 1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TR Rising Slew = VIH(ac)min - VREF delta TR
delta TF Falling Slew = VREF - VIL(ac) max delta TF
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Feb. 2005
10
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Note 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Crossing point
VIX or VOX
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol VOX (ac) Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Rev. 1.0 / Feb. 2005
11
1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS
Symbol VOTR Notes: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 0.5 * VDDQ Units V Notes 1
OUTPUT DC CURRENT DRIVE
Symbol IOH(dc) IOL(dc) Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement.
Rev. 1.0 / Feb. 2005
12
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz )
256MB : HYMP532S64[P]6
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 12 27 25 6.0 Max 15 30 32 7.5 Unit pF pF pF pF
512MB : HYMP564S64[P]8
Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 13 24 23 5 Max 21 38 40 8 Unit pF pF pF pF
512MB : HYMP564S64[P]6
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 17 22 28.5 10.0 Max 20 25 37.0 12.0 Unit pF pF pF pF
1GB : HYMP512S64M[P]8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Symbol CCK CI1 CI2 CIO Min 25 32 47 16 Max 49 58 96 20 Unit pF pF pF pF
Rev. 1.0 / Feb. 2005
13
1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC)
256MB, 32M x 64 SO- DIMM : HYMP532S64[P]6
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 E3(DDR2 400@CL 3) 500 540 24 140 160 80 20 260 600 720 660 22 12 1320 C4(DDR2 533@CL 4) 520 560 28 160 180 100 24 300 760 880 700 22 12 1320 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note
512MB, 64M x 64 SO- DIMM : HYMP564S64[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 Notes: 1. IDD6 current values are guaranted up to Tcase of 85 max. E3(DDR2 400@CL3) 640 720 48 280 320 160 40 440 1040 1200 1320 44 32 1760 C4(DDR2 533@CL 4) 720 800 56 320 360 200 48 520 1280 1440 1400 44 32 1760 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note
Rev. 1.0 / Feb. 2005
14
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
512MB, 64M x 64 SO - DIMM : HYMP564S64[P]6
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 E3(DDR2 400@CL 3) 760 800 48 280 320 160 40 520 860 980 920 44 32 1580 C4(DDR2 533@CL 4) 820 860 56 320 360 200 48 600 1060 1180 1000 44 32 1620 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note
1GB, 128M x 64 SO - DIMM : HYMP112S64M[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 Notes: 1. IDD6 current values are guaranted up to Tcase of 85 max. E3(DDR2 400@CL 3) 1080 1160 96 560 640 320 80 880 1480 1640 1760 88 64 2200 C4(DDR2 533@CL 4) 1240 1320 112 640 720 400 96 1040 1800 1960 1920 88 64 2280 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 1 note
Rev. 1.0 / Feb. 2005
15
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD Meauarement Conditions
Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1 ING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 max. Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Units mA
IDD1
mA mA mA mA mA mA mA
IDD2P IDD2Q IDD2N
IDD3P
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.0 / Feb. 2005
16
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS DDR2-533 (C4) 4-4-4 min 4 15 15 60 45 DDR2-400 (E3) 3-3-3 min 3 15 15 55 40 ns ns ns ns ns Unit
AC Timing Parameters by Speed Grade
Parameter Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input setup time DQ and DM input hold time DQ and DM input setup time(single-ended strobe) DQ and DM input hold time(single-ended strobe) Control & Address input Pulse Width for each input DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Rev. 1.0 / Feb. 2005 Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tDS1 tDH1 tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 tAC max tAC max tAC max 350 450 +0.25 0.6 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 tAC max tAC max tAC max 300 400 +0.25 0.6 tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK 17 DDR2-400 Min -600 -500 0.45 0.45 min (tCL,tCH) 5000 275 150 Max 600 500 0.55 0.55 8000 DDR2-533 Min -500 -450 0.45 0.45 min (tCL,tCH) 3750 225 100 Max 500 450 0.55 0.55 8000 Unit Note ps ns CK CK ns ps ps ps 1 1
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- Continued Parameter Address and control input setup time Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval Notes: 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS12[8/16]21(L)F). 2. 0C TCASE 85C 3. 85C TCASE 95C
t
Symbol tIS tIH tRPRE tRPST tRFC tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
t t
DDR2-400 Min 350 475 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 2 tAC(max)+ 1 2tCK+tAC( max)+1 2.5 tAC(max)+ 0.6 2.5tCK+tA C(max)+1 Max 1.1 0.6 -
DDR2-533 Min 250 375 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 2 tAC(max)+ 1 2tCK+tAC( max)+1 2.5 tAC(max)+ 0.6 2.5tCK+tA C(max)+1 Max 1.1 0.6 -
Unit Note ps ps tCK tCK ns ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3
CKE
AOND
tAON
tAONPD t
AOFD
t
AOF
AOFPD
tANPD tAXPD tOIT tDelay tREFI tREFI
12
12
Rev. 1.0 / Feb. 2005
18
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
32Mx64 - HYMP532S64[P]6
Front
67.60
20.00 Min
Side
3.80 max
4.00 +/-0.10
30.00
(Front)
20.00
PIN 1 PIN 39 PIN 41 PIN 199
1.00 0.10
6.00
11.40 2.70 4.20
2.45
47.40
11.40 2.40
Back
4.20
PIN 40
47.40
PIN 2
PIN 42
PIN 200
note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.0 / Feb. 2005
19
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
64Mx64 - HYMP564S64[P]8
Front
67.60
20.00 Min
Side
4.00 +/-0.10
3.8 max
30.00
(Front)
20.00
PIN 1 PIN 39 PIN 41 PIN 199
1.00 0.10
6.00
11.40 2.70 4.20
2.45
11.40 2.40
Back
4.20
PIN 40
47.40
PIN 2
PIN 42
PIN 200
note: note: 1. all dimension Units are millimeters. 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard. 2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.0 / Feb. 2005
20
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
64Mx64 - HYMP564S64[P]6
Front
67.60
20.00 Min
Side
3.80 max
4.00 +/-0.10
30.00
(Front)
20.00
PIN 1 PIN 39 PIN 41 PIN 199
1.00 0.10
6.00
11.40 2.70 4.20
2.45
47.40
11.40 2.40
Back
4.20
PIN 40
47.40
PIN 2
PIN 42
PIN 200
note: 1. all dimension units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.0 / Feb. 2005
21
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
128Mx64 - HYMP112S64M[P]8
Front
67.60
Side
3.8 max
20.00 Min
4.00 +/-0.10
30.00
20.00
PIN 1 PIN 39 PIN 41 PIN 199
11.40 2.70 4.20
2.45
1.00 +/- 0.10
6.00
11.40 2.40
Back
4.20
PIN 40
47.40
PIN 2
PIN 42
PIN 200
note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard.
Rev. 1.0 / Feb. 2005
22
1200pin Unbuffered DDR2 SDRAM SO-DIMMs REVISION HISTORY
Revision 1.0 History First Version Release - Data sheet coverage is changed from an individual module part to a component based module family. Date Feb.2005 Remark
Rev. 1.0 / Feb. 2005
23

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